In a MIPS pipeline, will there be a stall in the pipeline if the next instruction overwites the register of the previous register?

Question

For example if I have some MIPS pseudocode:

LW  R2, array(R1)   //R2 = array[1] = 4
SUB R2, R3, R1      //R2 = R3 - R1

Where R1 = 1, R2 = 2, R3 = 3, array[1] = 4

I understand that a stall would occur, and forwarding after MEM to EX of SUB instruction would be necessary if R2 was used in the calculation in the SUB instruction. However, in this case where the R2 register is overwritten anyways and it is not being used in the calculation, would it be necessary to stall the pipeline? Then is it necessary to even have this load instruction at the start?

I have tried searching for examples online but I couldn't find an example with this order of instructions. From my understanding of it, there shouldn't be a stall. However, I am a bit confused and needed some pointers.

Answer 1

The stall and forward caused by a the load-use delay is detected by the processor in the situation where there is a Read-After-Write hazard.

Thus, when there is no RAW hazard, there is no stall and no forward.

So, the following runs at full speed:

lw r2,4(r1)
addi r1, r1, 4

The standard MIPS 5-stage pipeline has no concept of Write-After-Read hazards (it doesn't have that hazard so it isn't looking for that situation or that hazard).

However, in this case where the R2 register is overwritten anyways and it is not being used in the calculation, would it be necessary to stall the pipeline?

No, in that sense, your sequence is no different from mine in that both will run at full speed without stall or forward.

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Then is it necessary to even have this load instruction at the start?

No, it is useless.

The only possible architectural purpose could be to test the resulting memory address to see if it causes a fault.  From a micro-architectural perspective, it might have side effects on the cache.

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FYI, lw r2,array(r1) is most likely a pseudo instruction, in particular if array is a global data label for the array (in the default memory configuration).  When dealing with pipeline hazards, probably best to stick with real MIPS instructions, since that pseudo instruction is expanded by the assembler into 2-3 real instructions.  Of course, the last instruction will be a load, so in this particular case there is still a load followed by what comes next.