I tried enabling this rule and ran spyglass, (I have 2 clocks of same frequency and phase). Still I'm getting a errors in cdc_verify saying data hold check failed in fast to slow clock transfer even though clocks are of same frequency.
Can anyone help me out here, do I have to add any parameter to let the tool know that they are of same frequency apart from .sgdc constraint?
I could eliminate some error using fa_holdmargin, but I'm not sure that it's a right way of doing things.