Error in the code I am unable to solve it and i am unable to prevent the error

Question

I am getting mixed port connection problem can anybody help me

I was trying to instantiate the previous module into the new module

.data_out(level1_1_out), 
.data_in(data_in1), 
.Cx(Cx1), 
.clk(clk) 

and

.data_out(level1_2_out),
.Data_In(data_in2), 
.Cx(Cx2), 
.clk(clk) 
.Sum(data_out), 
.A(level1_1_out), 
.B(level1_2_out)

Answer 1

There is a missing comma in the posted code:

.data_out(level1_2_out),
.Data_In(data_in2), 
.Cx(Cx2),
.clk(clk)  // **missing comma here** 
.Sum(data_out), 
.A(level1_1_out), 
.B(level1_2_out)

Also: Verilog is case sensitive.

The posted code uses mixed case names in an inconsistent manner. For example there is a port called data_out and another called Data_In and another called Sum (at least 3 different ways of naming in the post). It would be very easy to make a mistake on these names (because of the inconsistent use of case). If the name on the instance does not exactly match the name on the corresponding module, then compile errors are produced.

I recommend using a consistent and predicable style for naming.
For example use all lower case for the port names.