space is required between number and unit name

Question

I am full newbie in VHDL and I try to compile programs from this video https://www.youtube.com/watch?v=j9hya97kRJA

Here is the Makefile

GHDL=ghdl
FLAGS="--std=93"

all:
    @$(GHDL) -a $(FLAGS) --ieee=synopsys sevenseg_test.vhd sevenseg.vhd
    @$(GHDL) -e $(FLAGS) sevenseg_test
    @$(GHDL) -r $(FLAGS) sevenseg_test --wave=wave.ghw --stop-time=1us

Here is the file sevenseg_test.vhd:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sevenseg_test is
end;

architecture sim of sevenseg_test is

component sevenseg is
    port(
    S : in unsigned(3 downto 0);
    segments : out std_logic_vector(6 downto 0)
    );
end component;

signal S : unsigned(3 downto 0) := 4d"0";
signal segments : std_logic_vector(6 downto 0);

begin
dut : sevenseg port map(S, segments);
process begin
    for i in 0 to 15 loop
    S <= to_unsigned(i,4);
    wait for 10 ns;
    end loop;
    wait;
end process;

end sim;

First, I had this bug sevenseg_test.vhd:3:10:error: unit "numeric_std" not found in library "ieee" and I found that the solution is to add --ieee=synopsys in the command line on the Makefile. However I had to change the FLAGS from std=08 to --std=93 in order to make it works. But I have still this issue : sevenseg_test.vhd:17:37:error: space is required between number and unit name. When I check the line 17 row 37 it's between the 4 and the d in the code signal S : unsigned(3 downto 0) := 4d"0";. But it's normal to have 4d"0" in a vhdl code. I guess, maybe it's because I changed std=08 to --std=93. How can I solve the problem so as to compile the code ?