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My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

score 48 · Answer 1 · 2024-03-25T16:09:56.307000

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My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

48 views Asked by user23793022 At 25 March 2024 at 16:09

score 59 · Answer 2 · 2024-03-02T11:47:28.533000

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401 views Asked by Jim Lewis At 25 May 2022 at 02:40

score 122 · Answer 11 · 2022-04-15T03:17:16.023000

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122 views Asked by Mahmoud Abdel-Rahman At 15 April 2022 at 03:17

score 551 · Answer 12 · 2022-03-08T17:41:09.963000

Using Unisim with GHDL: vital_timing and vital_primitives not found in ieee library

551 views Asked by Theodore Norvell At 08 March 2022 at 17:41

score 313 · Answer 13 · 2022-03-02T23:29:20.300000

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313 views Asked by Mahmoud Abdel-Rahman At 02 March 2022 at 23:29

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space is required between number and unit name

374 views Asked by Student_in_computer_science At 18 January 2022 at 18:15

score 206 · Answer 15 · 2022-01-11T18:30:54.540000

ghdl never terminates and I don't know, why

206 views Asked by BitTickler At 11 January 2022 at 18:30

score 160 · Answer 16 · 2022-01-02T16:27:49.773000

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160 views Asked by Ibtehaj Khan At 02 January 2022 at 16:27

score 340 · Answer 17 · 2021-12-11T19:36:03.023000

VHDL AND operator usage " no function declarations for operator "and""

340 views Asked by Giorgi Aptsiauri At 11 December 2021 at 19:36

score 282 · Answer 18 · 2021-09-16T10:52:35.700000

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282 views Asked by dina At 16 September 2021 at 10:52

score 768 · Answer 19 · 2021-07-10T17:51:49.727000

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768 views Asked by dina At 10 July 2021 at 17:51

score 197 · Answer 20 · 2021-06-04T21:31:41.817000

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197 views Asked by mans At 04 June 2021 at 21:31

TechQA.

List Question

My VHDL ALU code fails to output the result of addition, but outputs the result of subtraction just fine?

VHDL/GHDL: Why does port name hide entity?

VHDL program's (Design+Testbench) run time is 0 sec

VHDL when running ghdl -r my testbench is getting stuck after passing two values

GHDL cannot find function defined in package

Could not find gnatmake binary after MacOS installation

vhdl: Why is aggregate assignment not allowed in this context?

VHDL: Mealy FSM not producing state changes at clock edges?

VHDL declaration expression cannot contain relational operator?

Redirecting output of tcl proc to file and output (like tee) Part 2

Unable to output data entered into a register

Using Unisim with GHDL: vital_timing and vital_primitives not found in ieee library

Unable to output data from ram memory address

space is required between number and unit name

ghdl never terminates and I don't know, why

Unable to synthesize code. GHDL throws an array bounds error

VHDL AND operator usage " no function declarations for operator "and""

purpose of command in makefile

GHDL -fsynopsys and -fexplicit options

error running ghdl sample dlx implementation

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