Scaling delay values in Design compiler topographical

Question

I want to scale delay values in TLU plus file to zero . How can we achieve that in design compiler topographical mode. How can we scale delay values to zero of TLU plus file in DC topo

Answer 1

Check "Assessing Design and Constraint Feasibility in Mapped Designs" on User Guide. You can use:

   set_zero_interconnect_delay_mode true