Exporting part of a circuit from a circuit defined as structural netlist in verilog

Question

I have a gate-level structual netlist of a design with 40,000 gates and 5000 flipflops in verilog. It is a flattened netlist with no sub-circuits inside. I would like to extract another netlist from this large netlist by deleting a few flip-flops and logic gates. The exported netlist should also be in verilog. I would like to know if an existing tool can do it.

Answer 1

You may use synthesis tools like Design Compiler (from Synopsys) or RTL compiler (from Cadence) to import the netlist, delete gates (e.g. from a tcl-script) and write out the modified netlist.

I'm sure that there are also lots of other tools that can be used for this purpose, so it also depends on your availability of these tools, and of course preferences in terms of which tools you know how to use.

Answer 2

Once the netlist is imported by Design Compiler, it's possible to delete any flip-flop or gate. Here is a simple example.

remove_cell {U1/reg1}

The following command helps to search for cells in the netlist.

get_cells "U1/reg*"