My question is about using generate a synthesizable divide by 2 clock and corresponding reset in verilog.
We can generate a divide by 2 clock as below using verilog
module frquency_divider_by2(
input rst_n,
input clk_rx,
output reg clk_tx
);
always @ (posedge clk_rx) begin
if (~rst_n) begin
clk_tx <= 1'b0;
end
else begin
clk_tx <= ~clk_tx;
end
end
endmodule
My question is how to generate corresponding reset(to be used by flops using clk_tx) using rst_n
Can any one help me for the same.
I appreciate your help
To async apply the reset and release after two positive edges of
clk_tx
. Waiting 2 positive edges stops the reset from being low for fractions of a clock period.For a synchronous reset you would need to check if it was low for any section of the faster clock, during synthesis you would need to check the cdc (clock domain crossing).