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Gate-Level Sim: Hold time violation between testbench and first registers?

score 48 · Answer 1 · 2024-03-15T23:13:34.310000

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Gate-Level Sim: Hold time violation between testbench and first registers?

48 views Asked by Abarajithan At 15 March 2024 at 23:13

score 23 · Answer 2 · 2024-01-25T16:23:29.780000

PRIMETIME | Issue linking hierarchal netlist

23 views Asked by Ani At 25 January 2024 at 16:23

score 107 · Answer 3 · 2023-03-22T22:01:40.750000

STA of 2 clocks with the same frequency

107 views Asked by shaiko At 22 March 2023 at 22:01

score 660 · Answer 4 · 2023-01-04T02:08:18.687000

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simvision tool?

660 views Asked by user20923807 At 04 January 2023 at 02:08

score 83 · Answer 5 · 2022-07-24T16:04:34.980000

-> operator in the middle of a property

83 views Asked by CCRCCR At 24 July 2022 at 16:04

score 604 · Answer 6 · 2022-07-10T21:53:43.957000

Where does the third dimension (as in 4x4x4) of tensor cores come from?

604 views Asked by Alfred At 10 July 2022 at 21:53

score 501 · Answer 7 · 2022-06-22T17:14:32.690000

SystemVerilog Assertion does not fail when it should

501 views Asked by CCRCCR At 22 June 2022 at 17:14

score 539 · Answer 8 · 2022-06-10T17:51:27.993000

SystemVerilog : Port connection based on parameter

539 views Asked by Wynn At 10 June 2022 at 17:51

score 101 · Answer 9 · 2022-01-06T10:56:58.363000

Why this process is executed when the simulation starts

101 views Asked by Hao Alessandro At 06 January 2022 at 10:56

score 75 · Answer 10 · 2021-10-19T13:54:03.010000

What does Trace Enable mean in Lauterbach?

75 views Asked by QTip At 19 October 2021 at 13:54

score 3170 · Answer 11 · 2021-04-17T18:13:21.447000

Asynchronous FIFO depth calculation

3.1k views Asked by Kun liu At 17 April 2021 at 18:13

score 1617 · Answer 12 · 2021-02-20T00:59:52.343000

Systemverilog function synthesis - automatic vs static

1.6k views Asked by shaiko At 20 February 2021 at 00:59

score 1192 · Answer 13 · 2021-02-10T12:38:01.573000

What is maximum size of the Queue in SystemVerilog?

1.1k views Asked by afzal junaidi At 10 February 2021 at 12:38

score 357 · Answer 14 · 2020-12-03T21:52:28.513000

Using firmware on ASIC simulation environment

357 views Asked by Marcus At 03 December 2020 at 21:52

score 1571 · Answer 15 · 2020-06-30T15:07:58.050000

SystemVerilog: writing into an array using a write pointer

1.5k views Asked by arandomuser At 30 June 2020 at 15:07

score 884 · Answer 16 · 2020-06-17T02:07:07.073000

How can I use genvar variable to access input signals?

884 views Asked by Tushar Garg At 17 June 2020 at 02:07

score 1190 · Answer 17 · 2019-07-09T11:18:00.457000

How to generate PREADY signal from slave in APB protocol?

1.1k views Asked by Payal At 09 July 2019 at 11:18

score 781 · Answer 18 · 2019-03-30T20:34:08.753000

Partial assignment to signal of record type when setting initial value

781 views Asked by andrsmllr At 30 March 2019 at 20:34

score 2710 · Answer 19 · 2019-03-30T20:28:11.777000

How to define default value for record type

2.7k views Asked by andrsmllr At 30 March 2019 at 20:28

score 1009 · Answer 20 · 2019-03-03T07:00:13.453000

How to generate a .db file from TSMC 65nm Standard Cell Library？

1k views Asked by chaotetung At 03 March 2019 at 07:00

TechQA.

List Question

Gate-Level Sim: Hold time violation between testbench and first registers?

PRIMETIME | Issue linking hierarchal netlist

STA of 2 clocks with the same frequency

Is it possible to display coverage of a specific bin within a coverpoint in a logfile using the simvision tool?

-> operator in the middle of a property

Where does the third dimension (as in 4x4x4) of tensor cores come from?

SystemVerilog Assertion does not fail when it should

SystemVerilog : Port connection based on parameter

Why this process is executed when the simulation starts

What does Trace Enable mean in Lauterbach?

Asynchronous FIFO depth calculation

Systemverilog function synthesis - automatic vs static

What is maximum size of the Queue in SystemVerilog?

Using firmware on ASIC simulation environment

SystemVerilog: writing into an array using a write pointer

How can I use genvar variable to access input signals?

How to generate PREADY signal from slave in APB protocol?

Partial assignment to signal of record type when setting initial value

How to define default value for record type

How to generate a .db file from TSMC 65nm Standard Cell Library？

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