Using firmware on ASIC simulation environment

Question

We are designing an ASIC that is based on an ARM CPU and multiple other hardware engines. These engines are controlled through memory mapped registers accessible by the CPU AHB port. Currently, we have simple tests written in C that are compiled, loaded and executed by the CPU RTL. Everything works fine, but, as expected, the CPU RTL slows down the simulation quite a lot, which makes difficult to run more complex C code to the test more extensively the rest of the design. Since we are not trying to verify the CPU RTL, I was wondering if a different approach would be possible.

We have most of the firmware already written in C, which is used for FPGA prototyping. The firmware accesses the memory mapped registers using the macros MemRead and MemWrite, which can be easily substituted by a function call or something similar. The approach would be:

1. Remove the CPU RTL from the design
2. Create a shim that is invoked by the MemRead and MemWrite C calls that would generate AHB requests to the design AHB slave port left disconnected by the CPU removal
3. Compile the C based firmware, RTL design (minus the CPU) and testbench with the simulator (Cadence irun, in our case)
4. Run the simulation

Is this even possible? Has anyone tried this approach? Any suggestions on how to come up with the "shim" between the C code firmware and the Verilog testbench and design?

Thank you,

Marcus.