Debugging module internals in Chisel

Question

I have a complex module written in Chisel. I'm using chiseltest to verify its operation. The test is failing. I want to be able to inspect the module's internal wire values to debug what is going wrong. Since the PeekPokeTester only allows me to inspect the value of the io signals, how can I inspect the internal wires?

Here is an example:

import chisel3._

class MyModule extends Module {
  val io = IO(new Bundle {
    val a = Input(Bool())
    val b = Input(Bool())
    val c = Input(Bool())
    val d = Output(Bool())
  })

  val i = Wire(Bool())
  i := io.a ^ io.b

  io.d := i | io.c
}

import chisel3._
import chisel3.tester._
import org.scalatest.FreeSpec

class MyModuleTest extends FreeSpec with ChiselScalatestTester {
  "MyModule should work properly" in {
    test(new MyModule) { dut =>
      dut.io.a.poke(true.B)
      dut.io.b.poke(false.B)
      dut.io.c.poke(false.B)
      dut.i.expect(true.B)  // This line throws a java.util.NoSuchElementException
                            // : key not found: Bool(Wire in MyModule)
    }
  }
}

How can I inspect the intermediate value "i"?

Answer 1

There's a few ways to do this.

1 ) Turn on VCD output by adding an annotation to your test, as in

import chiseltest.experimental.TestOptionBuilder._
import treadle._
...
test(new MyModule).withAnnotations(Seq(WriteVcdAnnotation)) { dut =>

The .vcd file will be placed in the relevant test_run_dir/ you can view it with GtkWave or similar

2 ) add printf statements to your module.

3 ) There is a simulation shell in the Treadle Repo that allows you to peek poke and step based on a firrtl file (the firrtl file should be in the same test_run_dir/ directory as above). There is A bit of documentation here

Good luck!