From 8.2 Load-Reserved/Store-Conditional Instructions chapter in RISC-V's unprivileged ISA Manual,
LR.W loads a word from the address in rs1, places the sign-extended value in rd, and registers a reservation set—a set of bytes that subsumes the bytes in the addressed word. SC.W conditionally writes a word in rs2 to the address in rs1: the SC.W succeeds only if the reservation is still valid and the reservation set contains the bytes being written.
What's the reservation in the description? How is it implemented in hardware? How does a Hart know if the reservation has been invalidated by another Hart?