verilog ripple alu .. got 'x' for slt operation

Question

I'm trying to create a ripple alu from one bit alu,

every thing is working fine except for the slt operation

it's implemented like so, for the one bit alu there is input 'less'

it's set to zero except for the LSB, it's got its vlaue from MSB of the subtractoin

one_bit_alu alu0 (.op(op), .a(a[0]), .b(b[0]), .cin(1'b0 ),    .less(set),  .r(z[0]), .cout(carry[0]));               
one_bit_alu alu1 (.op(op), .a(a[1]), .b(b[1]), .cin(carry[0]), .less(1'b0), .r(z[1]), .cout(carry[1]));
one_bit_alu alu2 (.op(op), .a(a[2]), .b(b[2]), .cin(carry[1]), .less(1'b0), .r(z[2]), .cout(carry[2]));
one_bit_alu alu3 (.op(op), .a(a[3]), .b(b[3]), .cin(carry[2]), .less(1'b0), .r(z[3]), .cout(carry[3]));
one_bit_alu alu4 (.op(op), .a(a[4]), .b(b[4]), .cin(carry[3]), .less(1'b0), .r(z[4]), .cout(carry[4]));
one_bit_alu alu5 (.op(op), .a(a[5]), .b(b[5]), .cin(carry[4]), .less(1'b0), .r(z[5]), .cout(carry[5]));
one_bit_alu alu6 (.op(op), .a(a[6]), .b(b[6]), .cin(carry[5]), .less(1'b0), .r(z[6]), .cout(carry[6]));
one_bit_alu alu7 (.op(op), .a(a[7]), .b(b[7]), .cin(carry[6]), .less(1'b0), .r(z[7]), .set(set));

here is the logic of the 'set' signal in the one_bit_alu module

full_subtractor  subtract(.d(subOP), .a(b), .b(a), .Bor_in(cin), .Bor_out(subOP_bout));
and (set, subOP, 1'b1);

it seems that every thing is fine but i got 'x' instead !

=================================
one_bit_alu module

`include "../lib/mux_16to1.v"
`include "../lib/full_adder.v"
`include "../lib/full_subtractor.v"

module one_bit_alu (
  input  [3:0] op,
  input  a, b, cin, less, sub,
  output r, cout, bout, set
  );

wire int0, int1, int2, int3, addOP, subOP, addOP_cout, subOP_bout;
and (int0 , a, b);
or  (int1  , a, b);
xor (int2 , a, b);
nor (int3, a, b);

xor (xorB, b, sub);

full_adder       add     (.sum(addOP), .a(a), .b(b), .cin(cin), .cout(addOP_cout));
full_subtractor  subtract(.d  (subOP), .a(b), .b(a), .Bor_in(cin), .Bor_out(subOP_bout));

and (set, subOP, 1'b1);

mux_16to1 mux0(
  .s  (op   ),
  .i0 (int0 ),
  .i1 (int1 ),
  .i2 (addOP),
  .i6 (subOP),
  .i7 (less ),
  .i12(int3 ),
  .z  (r    )
);

mux_16to1 mux1(
  .s(op),
  .i2(addOP_cout),
  .i6(subOP_bout),
  .z(cout));
endmodule

full_subtractor module

module full_subtractor (
  output Bor_out, d,
  input a, b, Bor_in
  );

wire int1, int2, int3, int4, b_bar;

// d = (a xor b) xor Bor_in
xor (int1, a, b);
xor (d, int1, Bor_in);

// Bor_out = ((a xor b)' and Bor_in) or (a and b')
not (int2, int1);
and (int3, int2, Bor_in); //(a xor b)' and Bor_in
not (b_bar, b);
and (int4, b_bar, a); //a and b'
or  (Bor_out, int4, int3);

endmodule

Answer 1

Found it!

the stl operation depends on the subtraction operation, and in my design I made a mux for the cout to take it either from the adder or the subtractor, depending on the 'op', so I should output it for the stl operation as will, the mux1 will be like so

mux_16to1 mux1(
  .s(op),
  .i2(addOP_cout),
  .i6(subOP_bout),
  .i7(subOP_bout), //2 days to find this line!
  .z(cout));