Verilog contention with next signal

Question

I'm trying to implement the following code:

reg [7:0] next_busy;

always @* begin
    next_busy = busy; //default assignment

    if (condition determined by module input) begin
        next_busy[0]= 1'b1;
    end
end //always @*

always @(posedge clock) begin
    if (reset) begin
        busy <= 8'b0;
    end else begin
        busy <= next_busy;
    end
end //always @(posedge clock)

This works fine in simulation, but in synthesis there seems to be some sort of contention for the next_busy signal. That is, if busy isn't 1 (say the previous cycle had a reset), then it outputs an x (if input conditions are met). However, if busy was already 1 (and the input conditions are met), then next_busy gets assigned 1 correctly. So I'm just wondering is there a proper way of doing what I'm trying to do so that it also works in synthesis?

Answer 1

You typically include the reset in a sensitivity list for flip-flops. For active low resets always @(posedge clock or negedge reset)

In the example provided busy is not defined, assuming it is reg [7:0] busy;.

I would implement along the lines of:

reg [7:0] busy;

always @(posedge clock or negedge reset) begin
    if (reset == 1'b0) begin
        busy    <= 8'b0;
    end
    else if (condition determined by module input) begin
        busy[0] <= 1'b1; // busy <= 8'b1;
    end
    else begin
        busy    <= next_busy;
    end
end //always @(posedge clock)