Verilog connect 2 module

Question

i have design a jk flip flop like this,

module jk_flip_flop(input pr,input clr,input j,input k,input clock,output reg q,output qNot);
assign qNot = (pr == 0 & clr == 0)?1:~q;
always @ (posedge clock or negedge clock)
    begin
        if(pr != 1 || clr != 1)begin
            case ({pr, clr})
                2'b01:  q<=1'b1; 
                2'b10:  q<=1'b0;
                2'b00:  q<=1'b1;
            endcase
        end
        else if(pr == 1 & clr == 1) begin
            case ({j, k})
            2'b00: q <= q; 
            2'b01:  q<=1'b0;
            2'b10: q<=1'b1;
            endcase
        end
        if(pr == 1 & clr == 1 & j == 1 & k == 1 & clock == 1)
            q <= ~q;
    end
endmodule

I want to implementing a divede by 5 counter, i need to use three jk flip flop to do that, how should i use this module again and again, i mean how should i connect the output of previous flip flop to the next

Answer 1

Something like this:

module something (input A, input B, output C)
...
endmodule

wire same_wire;
wire input_wire, output_wire;
wire middle_wire;

something some1(.A(same_wire), .B(input_wire), .C(middle_wire));
something some2(.A(same_wire), .B(middle_wire), .C(output_wire));
...