The uart on the FPGA is working half-heartedly. But it works correctly in simulation. Why is this so?

Question

I'm trying the dhrystone test on my risc-v processor in the FPGA. In the simulation, the fifo in the uart_tx module is working correctly. at first i was thinking maybe the tx wasn't being sent to the data what in fifo. But I typed uart_rx in testbench. But the testbench_rx was working perfectly. But I put my code in FPGA. I looking in uart console I just see 2 print(""); but when I send the code to FPGA. I see only 2 print commands from the Uart console. They skipped the print commands in between. In the simulation, this event works correctly. When I insert an FPGA it works half way. I'm running it at 20MHZ. I'm running 115200 baudrate. I using Zybo Z7-20 FPGA in this project

UART CONSOLE TEST

dhrstone's testcode's stage

Version Stage is working corrently in fifo

Timing and implementation

implementation warning

I expect my application to work correctly in the console. I don't know what's causing the problem.