This question might be funny (also i am very new to hypervisor).I have big confusion about SLAT (why it is required?).If i am not wrong SLAT(Second Level Address Translation) is used to do the address translation for guest virtual addr to actual physical address(guest virtual to host physical(correct me if am wrong, i.e: guest virt addr --> host virt addr --> host physical address). If HW not supporting SLAT then we have to use shadow page table to do the same (which is more overhead to CPU for doing additional translation in SW).
But my question is, can't we skip this page table handling by pass the actual physical memory to guest OS and let guest os handle the same (instead of using SLAT or shadow paging)? like UNMAP few memory banks (physical RAM address range) from Hypervisor and allocate the same to guest and launch that particular CPU with mmu off and exactly before start executing guest code. Code (might be kernel boot code) running in guest let it create its own page tables and enable MMU instead of having SLAT? When we required to stop the VM (at end guest opt should stop the mmu again), then we can restore the HV paging back to that particular CPU core and enable the MMU, right?
Is it any hole/problem in this approach (is this make sense?)? Can't we skip SLAT in virtualization?
(Kindly forgive me if my question not make any sense, as i am very new to virtualization :( )
Second-level address translation is needed for three reasons: to allow the guest view of memory to differ from the physical address map; to protect hypervisor memory and other guests’ memory from the guest; and to allow the hypervisor to intercept certain memory and MMIO accesses in order to virtualization the platform and devices.
If you start the guest with paging disabled, it will have full unrestricted access to all of memory (and MMIO space).
This is particularly important when running more than one guest. Each guest may expect its memory to start at address 0. Second-level address translation can convert each guest’s address 0 to a different physical memory address.