The recent game TIS-100 is centered around a rather interesting machine architecture, where the CPU consists of "nodes" which can communicate to their adjacent neighbours. I unfortunately cannot find an official link to the reference manual for public discussion, but in summary, each node supports a very simple ISA, but run on the same clock in parallel. Each node has two registers, an ACC
register and a BCK
secondary register. The reference manual says the CPU was designed for stream processing.
This struck me as a rather interesting and potentially useful design. Is this type of architecture used in the real world? It sort of feels like a mix between clocked processors and FPGAs.
This seems to be a simplified mix of different real architectures from different centuries. The instruction set of each node is similar to a simplified 8051 from the 1980ties. The TIS-100 nodes have a ACC and BCK register and the 8051 uses a A & D register. The A register is in most instructions and the D register, just like the BCK register can only be used in some rare cases.
Placing many rather simple nodes in a 2D-grid with communication ports to their neighbors is also something that has been done. This is usually called Manycore CPU. One example would be Tilera. However, the CPU cores used in such many core are simpler than current high performance CPUs, but not nearly as simple as the TIS-100 node. (or a 8051) Another example would be the Adapteva Epiphany IV.