Problem with reset Johson Counter Verilog

Question

I need to build the testbench and the design for a n-bit Johnson Counter, but I'm having problem with the reset of the circuit. The initial state should be 000, but I'm getting xxx. This happens for all n values. In this case, I'm testing with n = 3 (3 bits). All the results are right, as expected; the only problem is with the first value.

DESIGN

module johnsonCounter (clk, reset, out);
  parameter n = 3;
  input clk;
  input reset;
  output reg [n-1:0] out;
   
  
  genvar i;
  generate 
    for (i = n-1; i >= 0; i=i-1) begin: test
       always @ (posedge clk) begin
         out[i+1] <= out[i];
         if (!reset) 
           out <= 1;
         else begin
           out[0] <= ~out[n-1];   
        end
       end
    end
  endgenerate
 
endmodule

TESTBENCH

module tb;
  parameter n = 3;
  
  reg clk;
  reg reset;
  wire [n-1:0] out;
  
  //Instanciamento uut(Unity Under Test)
  johnsonCounter uut(clk, reset, out);
  
  //EPWave
  initial begin
    $dumpvars;
    $dumpfile("dump.vcd");
  end
  
  //
  always #10 clk = ~clk;
  
  initial begin
    {clk, reset} <= 0;

    $monitor ("Saidas = %b", out);
    repeat (2) @(posedge clk);
    reset <= 1;
    repeat (2*n) @(posedge clk);
    $finish;
  end
  
 
endmodule

#OUTPUTS

OUTPUT: 
# KERNEL: Saidas = xxx
# KERNEL: Saidas = 001
# KERNEL: Saidas = 011
# KERNEL: Saidas = 111
# KERNEL: Saidas = 110
# KERNEL: Saidas = 100
# KERNEL: Saidas = 000

EXPECTED OUTPUT:
# KERNEL: Saidas = 000
# KERNEL: Saidas = 001
# KERNEL: Saidas = 011
# KERNEL: Saidas = 111
# KERNEL: Saidas = 110
# KERNEL: Saidas = 100
# KERNEL: Saidas = 000

Answer 1

Use an asynchronous reset instead of a synchronous one. Change:

always @ (posedge clk) begin

to:

always @ (posedge clk or negedge reset) begin

This gets rid of the 1st xxx.