I am trying to boot linux on a zedboard and monitor all memory accesses through Programmable Logic. I am first trying to boot linux with a start address 0x40000000. I am following this article https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/460653138/Xilinx+Open+Source+Linux
Petalinux boot hangs at this point when I try to boot from SD card.
U-Boot 2020.01 (Oct 14 2020 - 11:49:27 +0000)
CPU: Zynq 7z020
Silicon: v3.1
Model: Zynq Zed Development Board
DRAM: ECC disabled 512 MiB
MMC: mmc@e0100000: 0
Loading Environment from SPI Flash... SF: Detected s25fl256s1 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
OK
In: serial@e0001000
Out: serial@e0001000
Err: serial@e0001000
Net:
ZYNQ GEM: e000b000, mdio bus e000b000, phyaddr 0, interface rgmii-id
eth0: ethernet@e000b000
Hit any key to stop autoboot: 0
Zynq>
Zynq>
Zynq>
Zynq>
Zynq>
Zynq>
Zynq> fatload mmc 0 0x3000000 uImage
4326032 bytes read in 255 ms (16.2 MiB/s)
Zynq> fatload mmc 0 0x2A00000 system.dtb
19816 bytes read in 20 ms (966.8 KiB/s)
Zynq> fatload mmc 0 0x2000000 rootfs.cpio.gz.u-boot
7157653 bytes read in 411 ms (16.6 MiB/s)
Zynq> bootm 0x3000000 0x2000000 0x2A00000
## Booting kernel from Legacy Image at 03000000 ...
Image Name: Linux-5.4.0-xilinx-v2020.1
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4325968 Bytes = 4.1 MiB
Load Address: 00200000
Entry Point: 00200000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 02000000 ...
Image Name: petalinux-image-minimal-zedboard
Image Type: ARM Linux RAMDisk Image (uncompressed)
Data Size: 7157589 Bytes = 6.8 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
## Flattened Device Tree blob at 02a00000
Booting using the fdt blob at 0x2a00000
Loading Kernel Image
Loading Ramdisk to 0e451000, end 0eb24755 ... OK
Using Device Tree in place at 02a00000, end 02a07d67
Starting kernel ...
Booting Linux on physical CPU 0x0
Linux version 5.4.0-xilinx-v2020.1 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP PREEMPT Wed Oct 14 11:48:47 UTC 2020
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
OF: fdt: Machine model: Zynq Zed Development Board
earlycon: cdns0 at MMIO 0xe0001000 (options '115200n8')
printk: bootconsole [cdns0] enabled
Memory policy: Data cache writealloc
cma: Reserved 16 MiB at 0x4f000000
percpu: Embedded 15 pages/cpu s31948 r8192 d21300 u61440
Built 1 zonelists, mobility grouping on. Total pages: 130496
Kernel command line: console=ttyPS0,115200 earlycon root=/dev/ram0 rw
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes, linear)
mem auto-init: stack:off, heap alloc:off, heap free:off
Memory: 484796K/524288K available (6144K kernel code, 217K rwdata, 1840K rodata, 1024K init, 131K bss, 23108K reserved, 16384K cma-reserved, 245760K highmem)
rcu: Preemptible hierarchical RCU implementation.
rcu: RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
Tasks RCU enabled.
rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
efuse mapped to (ptrval)
slcr mapped to (ptrval)
L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
L2C-310 erratum 769419 enabled
L2C-310 enabling early BRESP for Cortex-A9
L2C-310 full line of zeros enabled for Cortex-A9
L2C-310 ID prefetch enabled, offset 1 lines
L2C-310 dynamic clock gating enabled, standby mode enabled
L2C-310 cache controller enabled, 8 ways, 512 kB
L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
random: get_random_bytes called from start_kernel+0x260/0x440 with crng_init=0
zynq_clock_init: clkc starts at (ptrval)
Zynq clock init
sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
Switching to timer-based delay loop, resolution 3ns
Console: colour dummy device 80x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
CPU: Testing write buffer coherency: ok
CPU0: Spectre v2: using BPIALL workaround
CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
Setting up static identity map for 0x100000 - 0x100060
rcu: Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
CPU1: Spectre v2: using BPIALL workaround
smp: Brought up 1 node, 2 CPUs
SMP: Total of 2 processors activated (1333.33 BogoMIPS).
CPU: All CPU(s) started in SVC mode.
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 512 (order: 3, 32768 bytes, linear)
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
boot.scr scipt looks like this,
for boot_target in ${boot_targets};
do
if test "${boot_target}" = "jtag" ; then
bootm 0x00200000 0x04000000 0x00100000
exit;
fi
if test "${boot_target}" = "mmc0" || test "${boot_target}" = "mmc1" ; then
if test -e ${devtype} ${devnum}:${distro_bootpart} /uImage; then
fatload ${devtype} ${devnum}:${distro_bootpart} 0x43000000 uImage;;
fi
if test -e ${devtype} ${devnum}:${distro_bootpart} /system.dtb; then
fatload ${devtype} ${devnum}:${distro_bootpart} 0x42A00000 zynq-zed.dtb;
fi
if test -e ${devtype} ${devnum}:${distro_bootpart} /rootfs.cpio.gz.u-boot; then
fatload ${devtype} ${devnum}:${distro_bootpart} 0x42000000 uarm_ramdisk.image.gz;
bootm 0x43000000 0x42000000 0x42A00000
exit;
fi
bootm 0x43000000 - 0x42A00000
exit;
fi
done
Command to wrap:
mkimage -c none -A arm -T script -a 0x40000000 -e 0x40000000 -d out boot.scrHere's the steps I followed,
Download the below sources from the Xilinx git repository.
⦁ The Linux kernel with Xilinx patches and drivers
git clone https://github.com/Xilinx/linux-xlnx.git
⦁ The u-boot bootloader with Xilinx patches and drivers
git clone https://github.com/Xilinx/u-boot-xlnx.git
⦁ Device Tree compiler (required to build U-Boot)
git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.gitBuild FSBL: Built the First Stage Boot Loader (FSBL) application in the Vitis software platform, https://www.xilinx.com/html_docs/xilinx2020_1/vitis_doc/creatingnewzynqfsblappproj.html
Build Device Tree Compiler (dtc):
make
export PATH=`pwd`:$PATHEdited u-boot-xlnx/include/configs/zynq_common.h:
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenv dfu_alt_info " \
"${kernel_image} ram 0x43000000 0x500000\\\\;" \
"${devicetree_image} ram 0x42A00000 0x20000\\\\;" \
"${ramdisk_image} ram 0x42000000 0x600000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
cd to u-boot directory "cd u-boot-xlnx".
Add tool chain to path and then set tool chain
export CROSS_COMPILE=arm-linux-gnueabihf-
echo $CROSS_COMPILE
export ARCH=arm
echo $ARCH
To Configure sources for Zynq Zedboard and to build u boot for Zedboard:
make distclean
make xilinx_zynq_virt_defconfig
export DEVICE_TREE="zynq-zed"
makeTo make mkimage available in other steps, it is recommended to add the tools directory to your $PATH.
cd tools
export PATH=`pwd`:$PATH
Modifying the root filesystem:
Wrapping the image with a U-Boot header:
mkimage -A arm -T ramdisk -C gzip -a 0x40000000 -e 0x40000000 -d arm_ramdisk.image.gz uarm_ramdisk.image.gzBuilt kernel:
Made changes to the device tree in arch/arm/boot/dts
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
cd to u-boot directory "cd linux-xlnx/".
make ARCH=arm xilinx_zynq_defconfig
make ARCH=arm menuconfig
make ARCH=arm UIMAGE_LOADADDR=0x40008000 uImage
Built the Device tree:
make ARCH=arm zynq-zed.dtbCreated boot image,
the_ROM_image : {
[bootloader]fsbl.elf
u-boot.elf
[load=0x42a00000]zynq-zed.dtb
[load=0x42000000]uarm_ramdisk.image.gz
[load=0x43000000]uImage.bin // currently bootgen requires a file extension. this is just a renamed uImage
}
Generating the boot image:
bootgen -image boot.bif -arch zynq -o /<Path to store Boot.bin>/BOOT.binCopied BOOT.bin, u-boot.elf, fsbl.elf, zynq-zed.dtb and uarm_ramdisk.image.gz contents to the SD card. When i insert SD card to the board, I see just blank screen.
Kindly let me know what could be the issue here?
Regards,
Prasanna
you need put boot.scr to SD card as well.