Iverilog help combinational shift multiplier

Question

My code compiles but does not dump any dat file for gtkwave. I'm trying to implement a combination shift multiplier object. I don't think my tester is correct.

module combinational_mult(product,multiplier,multiplicand);
   input [31:0] multiplier;
   input[63:0] multiplicand;
   output reg [63:0] product;
   reg           c;
   reg [31:0]    m;  
   integer       i;

   always @( multiplier or multiplicand )
     begin
//initialize
        product[63:32] = 16'b0000_0000_0000_0000;
        product[32:16] = multiplier;
        m = multiplicand;
        c = 1'b0;


//add,shift algorithm  for unsigned multiplication.        
//following the notes.
         for(i=0; i<32; i=i+1)
           begin

        if(product[0]) {c,product[63:32]} = product[63:32] + m ;

         product[63:0] = {c,product[63:1]};
          c = 0;
      end              


  end    
endmodule

module tester(output reg [31:0] multiplier, output reg [63:0] multiplicand, output reg [63:0] product, output reg c, output reg i);



initial begin
i = 0;

$dumpfile("USAMv1.dat");
$dumpvars;

#10 multiplier = 16'b1101_1001_1101_1001;
multiplicand = 16'b0110_1010_1101_1000;
#50 $finish;

end
endmodule

module testbench;
 wire[31:0] multiplier;
wire[63:0] multiplicand;
wire[63:0] product;
wire c, i;

tester sim( multiplier, multiplicand, product, c, i);
combinational_mult dut ( product, multiplier, multiplicand);
endmodule 

Answer 1

I have created a version on EDA Playground which removes the tester and just runs a test program in the testbench.

I have renamed the dump.dat to dump.vcd to work with EDA Playground. which should launch the wave form window when run.

No real changes to the code other than moving test program to the testbench, and adding a second data point to the test vectors so they can be observed. otherwise the VCD finishes at the point they change.

module testbench;
 reg [31:0] multiplier;
 reg [63:0] multiplicand;

initial begin
  $dumpfile("dump.vcd");
  $dumpvars;

  #10ns;
  multiplier   = 16'b1101_1001_1101_1001;
  multiplicand = 16'b0110_1010_1101_1000;

  #50ns;
  multiplier   = 16'b0;
  multiplicand = 16'b0;

  $finish;
end

combinational_mult dut ( product, multiplier, multiplicand);
endmodule