Invalidation of an Exclusive cache line

Question

What happens if a CPU receives an invalidation message for a cache line in the Exclusive state? Can this message enter the invalidation queue?

If so, what happens if the same CPU attempts to to that cache line? Since the CPU would still think that is has the cache line Exclusive, he could just do the write and make a transition to Modified, without any bus transactions. When the invalidation queue will be flushed this write (and maybe other writes?) will be thrown away. Is this is a possible scenario in terms of MESI protocol?

Edit:

Consider this example:

void cpu0()
{
    a = 1;
    smp_wmb(); // write mem barrier, flush the store buffer
    b = 1;
}

void cpu1()
{
    while (b == 0) continue;
    //smp_rmb(); // read mem barrier, flush the invalidation queue
    a = 2;
}

Suppose that a, b is initially zero and a is held as Exclusive by CPU 1. Then suppose that CPU 0 executes cpu0() while CPU 1 executes cpu1().

Without the smp_rmb read memory barrier, is it possible that final value of a will be 1?

And if we add smp_rmb, will it bring the guarantees that the final value will be 2?