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Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

score 879 · Answer 1 · 2015-06-10 14:48:37

5

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879

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Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

879 views Asked by Andrew Russell At 10 June 2015 at 14:48

score 841 · Answer 2 · 2014-11-25 10:58:21

Performance cost of MESI protocol?

841 views Asked by user997112 At 25 November 2014 at 10:58

score 57 · Answer 3 · 2023-12-11 17:07:15

Invalidation of an Exclusive cache line

57 views Asked by klezki At 11 December 2023 at 17:07

score 113 · Answer 4 · 2023-12-14 17:10:53

How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?

113 views Asked by blonded04 At 14 December 2023 at 17:10

score 70 · Answer 5 · 2023-12-15 17:36:32

Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?

70 views Asked by k1r1t0 At 15 December 2023 at 17:36

score 100 · Answer 6 · 2022-04-04 16:19:50

Shortcomings of cache coherence alternative

100 views Asked by driewguy At 04 April 2022 at 16:19

score 185 · Answer 7 · 2021-04-25 22:36:58

Is synchronization faster on the same physical CPU core?

185 views Asked by Lingfeng Xiang At 25 April 2021 at 22:36

score 207 · Answer 8 · 2021-05-11 07:54:20

Can MESI protocol auto sync a variable value bewteen cpu cores?

207 views Asked by jean At 11 May 2021 at 07:54

score 218 · Answer 9 · 2021-05-19 10:40:23

MSI: When shared and invalid states can occur at the same time

218 views Asked by Diego Barreiro At 19 May 2021 at 10:40

score 3582 · Answer 10 · 2016-02-19 17:52:11

How does cache coherence work in multi-core and multi-processor architecture?

3.5k views Asked by Sergey At 19 February 2016 at 17:52

TechQA.

List Question

Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?

Performance cost of MESI protocol?

Invalidation of an Exclusive cache line

How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?

Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?

Shortcomings of cache coherence alternative

Is synchronization faster on the same physical CPU core?

Can MESI protocol auto sync a variable value bewteen cpu cores?

MSI: When shared and invalid states can occur at the same time

How does cache coherence work in multi-core and multi-processor architecture?

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