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10 TechQA 2024-12-25 03:47:38Why is the standard C# event invocation pattern thread-safe without a memory barrier or cache invalidation? What about similar code?
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Asked by Andrew Russell
Performance cost of MESI protocol?
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Asked by user997112
Invalidation of an Exclusive cache line
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Asked by klezki
How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?
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Asked by blonded04
Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?
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Asked by k1r1t0
Shortcomings of cache coherence alternative
110 views
Asked by driewguy
Is synchronization faster on the same physical CPU core?
192 views
Asked by Lingfeng Xiang
Can MESI protocol auto sync a variable value bewteen cpu cores?
213 views
Asked by jean
MSI: When shared and invalid states can occur at the same time
226 views
Asked by Diego Barreiro
How does cache coherence work in multi-core and multi-processor architecture?
3.5k views
Asked by Sergey