Let's say we have CPU-X and CPU-Y which have their own L1d caches. First, on CPU-X we execute simple read operation on memory location M that is stored in DRAM: after that CPU-X loads value stored in M into its own L1d cache and put it into (E) state (assume it uses MESI protocol for cache coherency).
Then CPU-Y execute lock cmpxchg on the same memory location M. According to Intel 9.1.4. "Effects of a LOCK Operation on Internal Processor Caches" section:
For the P6 and more recent processor families, if the area of memory being locked during a LOCK operation is cached in the processor that is performing the LOCK operation as write-back memory and is completely contained in a cache line, the processor may not assert the LOCK# signal on the bus. Instead, it will modify the memory location internally and allow it’s cache coherency mechanism to ensure that the operation is carried out atomically. This operation is called “cache locking.”
So, since the value of M isn't cached in CPU-Y's caches, it must assert the LOCK# signal on the bus, right? Then, will it load value stored in CPU-X's caches into its own L1d cache (or something else happen?)? If so, must CPU-X put its own value into (I) state?