How to port design implementations made on gem5 to a realtime RISCV hardware

Question

I have created a project on gem5 modifying the cache replacement policies I would like to port the design implemented on gem5 to a real-time RISCV processor. How do I do that should I first port it to something like Rocketchip and then port it to an FPGA board? Because the modifications I have made on gem5 are at the hardware level. please correct me if I am wrong ,I am new to this.