How to make sure that the hardware generated in the FPGA is correct for that particular piece of code?

Question

I was asked this question in an interview. The interviewer asked the question like " Suppose you have written a code for generating a clock of 250MHz in verilog and synthesized it. Now how will you make sure that the hardware generated will work for 250MHz before emulating it? " I have searched internet regarding this but couldn't find any answer.

Answer 1

• Some toolkits have post-PAR(place and route) simulations that simulate not only the logical behaviors but also the timing. Using post-PAR simulation you can verify if the circuit will fit the timing constraints.
• Another way of verifying timing is using timing constraints. Your software probably has some constraints editors that you can set a constraint for the desired output signal. Once defined the software will check the timing during mapping/place-and-route phase and report if it is met.

Answer 2

Sorry for posting as an answer, don't have reputation for a comment.

I think maybe the answer the interviewer wanted is to use a timing analyzer.

Define your constraints in an SDC like file and use the vendor timing analyzer to check that the 250MHz clock will indeed work in that given hardware.

Answer 3

Run your clock generating Verilog code on a simulator.

The FPGA vendors typically provide simulators with their synthesis tools; or you can use a free simulator, or commercial simulator from an EDA vendor.

Simulators let you look at all of the values of the signals in a design over time, displayed in an intuitive graphical user interface, enabling you to find and fix many problems before you deploy your code on the FPGA.

Answer 4

A netlist created by synthesis or PAR tool, should pass the main steps (not limited to them) below to be verified. FPGA tools have options to write out a gate-level netlist and export the tech library, so third party tools can also be used for these steps.

1) Static Timing Analysis (STA)

Verifies timing of the netlist regarding the timing constraints defined by the user. Xilinx and Intel (formerly Altera) have built-in tools in their design suites.

2) Formal/Logic Equivalence Checking

Compares the functionality of RTL and netlist. Since this is a formal process, there is no need to feed input vectors (e.g. testbench).

3) Gate-level simulations

Verifies both functionality and timing. Usually an SDF (Standard Delay Format) file is fed for timing data of the netlist. SDF can be created by synthesis, STA, or PAR tool.