How to make an array in 'verilog' (code inside)

Question

I want to make an array called 'a' and fill it with any binary numbers

and It's 1-D array my code must do as sw in mips (store word) 'm' the value that I want to store it in 's'

Thank you,

module ALU(m,s,control,out,zeroflag,array);

input [31:0] m,s;
input [7:0] control;
output reg [31:0] out;
output reg zeroflag;
reg a [0:2]; // this is the array

a[2] = 4'b0000; // filled it..
a[1] = 4'b1001;
a[0] = 4'b0110;

always @(m,s,control,out,zeroflag,array)
begin
case(control)
8'h2B :  if(s==8'h0) a[0] = m;
         out = a[0];
  else if(s==8'h1) a[1] = m;
         out = a[1];
  else             a[2] = m;
         out = a[2];

endcase
end

always @(out)
begin
if(out==0)
zeroflag <= 1;
else
zeroflag <= 0;
end
endmodule

//////////////////////////////////////////

module test;
reg [31:0] m,s;
reg [7:0] control;
wire [31:0] outpt;
wire zeroflag;

ALU rtypeoperations(m,s,control,outpt,zeroflag);
initial
begin
m=32'b0000; s=8'h0; control=8'h2B; //stores m value in array[0] if s=8'h0, stores m value in array[1] if s=8'h1, stores m value in array[2] if s=8'h2,
end

initial
begin
$monitor("At time = %0t ,result = %b, zero flag = %b ",$time ,outpt,zeroflag);
end
endmodule

Answer 1

I see a lot of problems in your code. Does this even compile?

First, your operations for filling the array needs to be inside an initial block.

initial begin
  a[2] = 4'b0000; // filled it..
  a[1] = 4'b1001;
  a[0] = 4'b0110;
end

Please note that initial blocks are allowed for FPGA rtl (FPGAs can have power on initial values for registers) and for behavioural (testbench) code, but not for ASICs.

Second, your always @(m,s,control,out,zeroflag,array) contains outputs in the sensitivity list. It should only be inputs.

Third -- you need some clocks in your code. Right now everything is combinational logic the way it's written.

Finally, learn to indent your code properly. Here's one suggestion for coding guidelines: https://github.com/NetFPGA/netfpga/wiki/VerilogCodingGuidelines