How to implement a schematic in vhdl code and converting the datatypes from std_logic to bit

Question

I tried to implement an adder which is way faster then the average RCA. Therefore I used the XILINX library and found one easy adder called adsu8. I want to embed it into my recent VHDL code. but therefore I have to stick to the data type BIT and BIT_VECTOR. Now every time I synthesise there pops out a bunch of warnings like this:

:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- entity of module
entity rca_8bit is
Port ( OP_A : in  BIT_VECTOR (7 downto 0);
       OP_B : in  BIT_VECTOR (7 downto 0);
       ADDSUB : in  BIT;
       SUM : out  BIT_VECTOR (7 downto 0);
          FLAGS : out BIT_VECTOR (4 downto 0));
end rca_8bit;

-- architecture describes behavior of module
architecture behavioral of rca_8bit is
-- sub-module is declared
component adsu8
    port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
             B : in  STD_LOGIC_VECTOR (7 downto 0);
             CI : in BIT;
             S : out  STD_LOGIC_VECTOR (7 downto 0); 
             CO : out  BIT;
             OFL : out BIT);
end component;
-- some code to avoid the blackbox warning message of 
--  component adsu8 which is implemented from schematics  
attribute box_type : string; 
attribute box_type of adsu8 : component is "black_box"; 

-- additional wires std_logic
signal SIG_A,SIG_B,SIG_S : STD_LOGIC_VECTOR (7 downto 0); 

-- additional wires bit
signal  SIG_SUM : BIT_VECTOR (7 downto 0);
signal  SIG_FLAGS :  BIT_VECTOR (4 downto 0);
signal  SIG_CO,SIG_OFL : BIT;


begin
-- instantiate and do port map
AS8 : adsu8 port map (SIG_A,SIG_B,ADDSUB,SIG_S,SIG_CO,SIG_OFL);

-- convert and forward std_logic to bit
SIG_A <= to_stdlogicvector(OP_A);
SIG_B <= to_stdlogicvector(OP_B);
SIG_SUM <= to_bitvector(SIG_S);

-- assign result
SUM <= SIG_SUM;
-- generate flags
SIG_FLAGS(0) <= SIG_SUM(7) xor SIG_FLAGS(1);            -- S (N xor V)
SIG_FLAGS(1) <= SIG_OFL;                                -- V
SIG_FLAGS(2) <= SIG_SUM(7);                             -- N (MSB = 0)
SIG_FLAGS(3) <= '1' when SIG_SUM = "00000000" else '0'; -- Z
SIG_FLAGS(4) <= SIG_CO;                                 -- C
-- assign flags
FLAGS <= SIG_FLAGS;

end behavioral;

I am not this experienced in VHDL but also not that less. But this problem confuses me and causes headache. I am grateful for any solution or information in the right direction.

Thanks in advance and best regards

Tobi