EDA Playground: No *.vcd file found. EPWave will not open

Question

I am trying to run the following VHDL code for a digital clock, but I am encountering an error message and I am not sure how to fix it.

This is the link to my code in EDA Playground

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--Top module which instantiates and connects together the 3 components:
--Digital clock, Binary to BCD converter, BCD to 7 segment code converter
entity digital_clock_topmodule is
    --frequency of the clock passed as a generic parameter.
    generic ( CLOCK_FREQ : integer := 50000000 ); 
    port (
        Clock : in std_logic;  --system clock
        reset : in std_logic;  --resets the time
        inc_secs : in std_logic;  --set a pulse here to increment the seconds by 1.
        inc_mins : in std_logic;  --set a pulse here to increment the minutes by 1.
        inc_hrs : in std_logic;  --set a pulse here to increment the hours by 1.
        secs_7seg1 : out unsigned(6 downto 0);  --seconds LSB digit
        secs_7seg10 : out unsigned(6 downto 0);  --seconds MSB digit
        mins_7seg1 : out unsigned(6 downto 0);  --minutes LSB digit
        mins_7seg10 : out unsigned(6 downto 0);  --minutes MSB digit
        hrs_7seg1 : out unsigned(6 downto 0);  --hours LSB digit
        hrs_7seg10 : out unsigned(6 downto 0)   --hours MSB digit
    );
end digital_clock_topmodule;

architecture Behavioral of digital_clock_topmodule is

    --Digital clock component
    COMPONENT digital_clock IS
        GENERIC ( CLOCK_FREQ : integer := 50000000 );
        PORT (
            Clock : IN std_logic;
            reset : IN std_logic;
            inc_secs : IN std_logic;
            inc_mins : IN std_logic;
            inc_hrs : IN std_logic;
            seconds : OUT unsigned(5 downto 0);
            minutes : OUT unsigned(5 downto 0);
            hours : OUT unsigned(4 downto 0)
        );
    END COMPONENT;
     
    --Binary to BCD converter component
    COMPONENT bin2bcd IS
        PORT (
            binary_in : IN unsigned(5 downto 0);
            bcd_out : OUT unsigned(7 downto 0)
        );
    END COMPONENT;
    
    --Function to convert a BCD digit into a 7 segment code
    --Source: https://vhdlguru.blogspot.com/2010/03/vhdl-code-for-bcd-to-7-segment-display.html
    --The function is created by converting the code from the above link.
    FUNCTION bcd2seg7( bcd_in : unsigned(3 downto 0) ) RETURN unsigned IS
        VARIABLE segment7 : unsigned(6 downto 0);
    BEGIN
        CASE bcd_in IS
            WHEN "0000" => segment7 :="0000001";  -- '0'
            WHEN "0001" => segment7 :="1001111";  -- '1'
            WHEN "0010" => segment7 :="0010010";  -- '2'
            WHEN "0011" => segment7 :="0000110";  -- '3'
            WHEN "0100" => segment7 :="1001100";  -- '4'
            WHEN "0101" => segment7 :="0100100";  -- '5'
            WHEN "0110" => segment7 :="0100000";  -- '6'
            WHEN "0111" => segment7 :="0001111";  -- '7'
            WHEN "1000" => segment7 :="0000000";  -- '8'
            WHEN "1001" => segment7 :="0000100";  -- '9'
            --nothing is displayed when a number more than 9 is given as input.
            WHEN OTHERS => segment7 :="1111111";
        END CASE;
        RETURN segment7;
    END bcd2seg7;

    --Declare internal signals   
    SIGNAL seconds : unsigned(5 downto 0);
    SIGNAL minutes : unsigned(5 downto 0);
    SIGNAL hours : unsigned(4 downto 0);
    SIGNAL bcd_secs, bcd_mins, bcd_hrs : unsigned(7 downto 0);
    SIGNAL hours_extended : unsigned(5 downto 0);

BEGIN

    -- Instantiate the Digital Clock component
    uut : digital_clock 
        GENERIC MAP ( CLOCK_FREQ => CLOCK_FREQ )
        PORT MAP (
            Clock => Clock,
            reset => reset,
            inc_secs => inc_secs,
            inc_mins => inc_mins,
            inc_hrs => inc_hrs,
            seconds => seconds,
            minutes => minutes,
            hours => hours
        );

    --convert binary to BCD for seconds
    bin2bcd_secs : bin2bcd 
        PORT MAP (
            binary_in => seconds,
            bcd_out => bcd_secs
        );

    --convert binary to BCD for minutes
    bin2bcd_mins : bin2bcd 
        PORT MAP (
            binary_in => minutes,
            bcd_out => bcd_mins
        );

    hours_extended <= '0' & hours;    --just make it the same size as seconds and minutes.
    --convert binary to BCD for hours
    bin2bcd_hrs : bin2bcd 
        PORT MAP (
            binary_in => hours_extended,
            bcd_out => bcd_hrs
        );
            
    --Call the bcd2seg7 function to convert each BCD digit into a format which can be used on the 7 segment display
    secs_7seg1 <= bcd2seg7( bcd_secs(3 downto 0) );
    secs_7seg10 <= bcd2seg7( bcd_secs(7 downto 4) );
    mins_7seg1 <= bcd2seg7( bcd_mins(3 downto 0) );
    mins_7seg10 <= bcd2seg7( bcd_mins(7 downto 4) );
    hrs_7seg1 <= bcd2seg7( bcd_hrs(3 downto 0) );
    hrs_7seg10 <= bcd2seg7( bcd_hrs(7 downto 4) );

END Behavioral;

When I try to run the code, I get an error message that says:

No *.vcd file found. EPWave will not open. Did you use `$dumpfile("dump.vcd"); $dumpvars;'? How can I fix it?

How can I fix this issue?

Answer 1

The problem is that you used the wrong settings in EDA Playground.

One way to fix it is to change the name of the "Top entity" in the left side panel from:

testbench

to:

tb_digitalClock

This link runs and shows waveforms.

---

When I hit "Run" on your link, the "Log" panel at the bottom showed these warning and error messages:

ELAB1 WARNING ELAB1_0026: "There is no default binding for component "digital_clock". 
(No entity named "digital_clock" was found)." "testbench.vhd" 53 0
COMP96 Compile success 0 Errors 2 Warnings  Analysis time :  10.0 [ms]
# Aldec, Inc. Riviera-PRO version 2022.04.117.8517 built for Linux64 on May 04, 2022.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2022 Aldec, Inc. All rights reserved.
# VSIM: Error: Unknown library unit 'testbench' specified.
# VSIM: Error: Simulation initialization failed.
Finding VCD file...
No *.vcd file found. EPWave will not open. 
Did you use '$dumpfile("dump.vcd"); $dumpvars;'?

The name of the entity in the "testbench.vhd" tab needs to match the name of the entity in the "Top entity" box in the left panel.