I am building a cache simulator for a intel core i7 but have a hard time finding the detailed specifications for the L1, L2 and L3 cache (shared). I need the Cacheblock size, cache size, associativity and so on... Can anyone point me in the good direction?
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Intel's Optimization guide describes most of the required specifications per architectural generation (you didn't specify which i7 you have, there are now several generations since Nehalem and up to Haswell).
Haswell, for e.g., would have -
Note that if you're building a simulator, you'll want to have as many of these feature as possible parametrized. There are also many other considerations you'll need to take into account that are explained there (for e.g. inclusiveness, write-back/write-through protocols, cache coherency protocols, etc..)