Are RISC-V SH and SB instructions allowed to communicate with the cache?

Question

Are risc-v instructions such as sb and sh allowed to access the cache? Or does it communicate directly with the main memory? I have seen the Wstrb event in main memory structures, but generally not in caches. Does this depend on whether the person is programming with Verilog? I don't ask because sw will already be 32 bit, but sb and sh confuse me.

I will program cache based on the answer given.

Answer 1

Cache should see informations about the operation such as address, store/load, width of the operation and store data. Caches make this strobe operation inside, by looking at the offset of the address and the width of the operation.

Answer 2

Narrow stores to cacheable memory might need to RMW the containing word of cache to update the ECC granule; most non-x86 microarchitectures do that, at least if the store buffer can't merge multiple stores into a full ECC word: See Are there any modern CPUs where a cached byte store is actually slower than a word store?

Evicting the cache line and bypassing cache would not be a normal design; programmers and compilers expect that byte stores are reasonably fast.

Same for unaligned word stores, which RISC-V requires to be supported. (But it allows support to be very slow, via trapping to a fault handler. IDK how many real RISC-V designs just trap vs. having some kind of hardware support for unaligned loads and/or stores.)