Why there are verilog verification files not in the form of module?

Question

Why are there Verilog verification files not in the form of a module? The files I see start with just initial begin, and some file names use the .inc extension.

Answer 1

It is common to include files of arbitrary content into Verilog modules. This is done using the `include compiler directive, as described in IEEE Std 1800-2012, section "22.4 `include":

The file inclusion (include) compiler directive is used to insert the entire contents of a source file in another file during compilation. The result is as though the contents of the included source file appear in place of the `include compiler directive.

It can be useful for sharing common code between different modules: parameters, define macros, tasks, functions, etc.

In general, the .inc file extension is not special. It may be a convention used by certain simulation tools.