Previous versions of the Intel® 64 and IA-32 Architectures Optimization Reference Manual have contained this Coding Rule:
Assembly/Compiler Coding Rule 12. (M impact, H generality)
All branch targets should be 16-byte aligned.
The May 2020 version does not have this rule. Why was it removed?
Alignment to 16 bytes comes with a cost as discussed here on the Linux Kernel Mailing List. But it is a long standing rule and ARM has the same rule for its microarchitectures.
Consider aligning subroutine entry points and branch targets to quadword (16 byte) boundaries.
AMD's Software Optimization Guide for AMD Family 17h Processors says:
Having 16 byte aligned branch targets gets maximum picker throughput and avoids end-of-cacheline short op cache (OC) entries.