I'm currently reading the Intel 64 and IA-32 Architectures Software Developer's Manual and I have a question regarding paging.
My question is: In a 32-bit paging environment with a 4KB page size, what are the roles of the PWT and PCD bits in CR3? Also, what are the functions of the PWT and PCD bits in PDEs and PTEs?
The manual mentions that these two bits in CR3 are "indirectly determine the memory type used to access the page directory during linear address translation."
My understanding is that when CR3.PWT=1 and CR3.PCD=0, it means the memory type of entries in the page directory is Write Through. So, if the OS updates an address or flag in a PDE, then the updated PDE will be stored back simultaneously in both the cache and memory