VHDL simulation won't run

Question

I have just picked up The Designer's Guide to VHDL and I am working through the exercises in the first chapter. I ran into an issue with my 2 bit multiplexer that I don't understand.

The code for my multiplexer:

library ieee;
use ieee.std_logic_1164.all;

entity multi2 is
        port
        (
            a,b     : in bit;
            sel     : in boolean;
            z       : out bit   
        );
end multi2;

architecture behave of multi2 is

begin
    storage : process is
        variable stored_d0 : bit;
    begin
    wait for 1 ns;

    if sel then
        z <= a;
    else
        z <= b;
    end if;

    end process storage;
end architecture behave;

I can't figure out why I need the "wait for 1 ns;" line. If I move it to below the "end if" line the simulation won't work and I won't get my .vcd output from GHDL. Without the wait line, or it being in the wrong spot gives me an error in my vcd file about beginning and end time being the same.

Do I need wait statements in my process in order to work?

My test bench code is below:

    library ieee;
use ieee.std_logic_1164.all;

entity multi2_tb is
end multi2_tb;

architecture test of multi2_tb is
component multi2
    port
    (
        a,b     : in bit;
        sel     : in boolean;
        z       : out bit
    );
end component;

signal a,b       : bit;
signal sel       : boolean;
signal z         : bit;

begin
multiplexer2: multi2 port map (a => a, b => b, sel => sel, z => z);

process begin

    a <= '0';
    b <= '1';
    sel <= false;
    wait for 3 ns;

    a <= '0';
    b <= '1';
    sel <= true;
    wait for 3 ns;

    a <= '0';
    b <= '1';
    sel <= false;
    wait for 3 ns;


    assert false report "Reached end of test";
    wait;

    end process;
end test;