I'm using Modelsim command line simulation & producing WLF of all signals. Language is VHDL.
The problem is that, I've many signals defined in VHDL package, but those signals are not available in WLF after simulation is over.
Is there any command or modelsim.ini to be modified to dump package signals to WLF?
Given that you use the library from the top level of your simulation you can do:
or just
Just doing the following does not cause package signals to be included.