I have VHDL module with bidirectional port which nested in Top module. In testbanch I try to assign data to signal which connected to bidirectional port of Top. But assigned data don't propogate to nested module bidirectional port, I see assigned data only at signal of tb, not at port. Data from nested bidir port propogate to signal of tb sucsessfully. What is the cause of such behaviour?
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Bidirectional ports of nested and top modules must be connected without intermediate signals. In case of intermediate signal the construction will work like unidirectional.