verilog testbench - submodule array writing in a file

Question

I need to write an array in a file in verilog test bench. the array is declared as below in the module stage1.v (hierarchy picture attached)

wire [WIDTH-1:0] s1_res1_arr[0:LENGTH-1];

it is filled with certain values.

in my testbench i am writing like this

write_file = $fopen("stage1.txt"); 

for ( i = 0 ; i <= 255 ; i = i+1 )
  $fwrite(write_file,"%b \n",FFT_top/stage1/s1_res1_arr[i]);

modelsim is giving the following error

Failed to find 'FFT_top' in hierarchical name '/FFT_top'.
Failed to find 'stage1' in hierarchical name '/stage1'.
Failed to find 's1_res1_arr' in hierarchical name '/s1_res1_arr'.

Answer 1

Okay, I found it myself. It will be done as:

$fwrite(write_file1,"%b \n",uut.FFT_top.stage_1.s1_res1_arr[i]);