Verilog Synthesis Error : "Expecting Endmodule", when using `include directive

Question

I got "expecting endmodule" error when compile the try_main.sv rtl below. It seem to be rooted from the declaration of "t_five_bits i_comb_sig;" in try_top module. Once I commented out that declaration, the error is gone.

May I know how can I solve this error?

Thanks in advance :)

File name : bit5.svh

typedef struct {
    logic[2:0] three_bits  
    logic[1:0] two_bits
} t_five_bits;

File name : try_main.sv

`include "bit5.svh"
module try_top ( 
    input logic clk,
    input logic sigA,
    input logic sigB,
    ouput logic sigC );

logic i_sigA;
logic i_sigB;
logic i_sigC;
t_five_bits i_comb_sig;

.
.
.

endmodule

Answer 1

You're missing some ;s after the struct member declarations. Change it to:

typedef struct {
    logic[2:0] three_bits;
    logic[1:0] two_bits;
} t_five_bits;