Verilog: Is there a way to make a generalized adder (variable width/number of inputs)?

Question

I am trying to write some verilog code that I would like to be reusable for an application that has a lot of addition with a varying number of inputs. Say I have a module:

module parameterizable_adder #( 
  parameter WIDTH = 16,
  parameter NUM_INPUTS = 16)( 
  input [NUM_INPUTS*WIDTH-1:0] in_data, output [NUM_INPUTS+WIDTH-1:0] out_data
);

  //treat this block as psuedo code
  integer i;
  for (i = 0; i < NUM_INPUTS; i = i + 1) begin
    out_data = out_data + in_data[i*WIDTH+WIDTH-1:i*WIDTH];
  end

endmodule

This is more or less what I want to do. Is there a way in verilog to do this and have it be synthesize-able? Ideally the for loop would be un-rolled and optimized so its not trying to do the addition in NUM_INPUTS-1 stages. Is this better suited for a generate statement?

Thanks

Answer 1

You do not need generate block for this

integer i;
reg [NUM_INPUTS+WIDTH:0] temp_data;
always @* begin
     temp_data = 0;
     for (i = 0; i < NUM_INPUTS; i = i + 1) 
       temp_data = temp_data + in_data[i*WIDTH +: WIDTH];
     out_data = temp_data;
    end