Verilog - Is it possible to create two vcd files during the same simulation

Question

I have to create two vcd files. One which starts at zero time and ends when a specific signal changes, and one which start right after.

Is it possible to do it with verilog?

Answer 1

The Verilog standard does not provide a way of doing this in one simulation. Your first simulation would run up until the specific signal changes creating your first VCD file. Your second simulation would have to start dumping to the second VCD file when the specific signal changes.

Some tools, like ModelSim/Questa, provide Tcl command line options for dumping to multiple VCD files. You would turn off dumping to the first VCD file at same time start dumping to the second VCD file. Please read your tools user manual.