Verilog FPGA poor placement for routing between IO pin and BUFG error?

60 views Asked by At

I've been encountering this error every time I have tried to run implementation of my modules on Verilog. I've looked into previous error flags related to this but the solutions aren't really working. I'll link my current .xdc file with it's constraints here.

Here's the error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clr_IBUF] >

clr_IBUF_inst (IBUF.O) is locked to IOB_X1Y48 and clr_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y14

From what I can understand, the error appears to be centered around my CLK100MHZ which is being used for my joystick input. I don't really understand why though, the W5 pin I've assigned from the reference with the official BASYS3 reference is correct as it is the only 100MHZ clock pin. Which means I doubt the error is because of the I/O assignment.

When I use the given constraint addition to demote this from an error to a warning, the implementation works and the bitstream is generated - but there is no VGA output and my program doesn't work. I'm not sure if this is related to this error or if it is because of some other reason. And as a result debugging has become a nightmare. For reference, I have an old bitstream of before I attempted to integrate my code with the joystick, and my code was giving a vga output then. So I'm not sure what could have broken it except for the fact that the clock signal isn't working. If anyone could provide any advice whatsoever I'd really appreciate it.

Here's my .xdc file:

set_property PACKAGE_PIN W5 [get_ports CLK100MHZ]
    set_property IOSTANDARD LVCMOS33 [get_ports CLK100MHZ]
    create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports CLK100MHZ]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {blue[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {blue[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {green[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {green[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {green[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {red[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {red[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {red[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN U16 [get_ports {LED[0]}]
set_property PACKAGE_PIN E19 [get_ports {LED[1]}]
set_property PACKAGE_PIN U19 [get_ports {LED[2]}]
set_property PACKAGE_PIN V19 [get_ports {LED[3]}]
set_property PACKAGE_PIN W18 [get_ports {LED[4]}]
set_property PACKAGE_PIN U15 [get_ports {LED[5]}]
set_property PACKAGE_PIN U14 [get_ports {LED[6]}]
set_property PACKAGE_PIN V14 [get_ports {LED[7]}]
set_property PACKAGE_PIN V13 [get_ports {LED[8]}]
set_property PACKAGE_PIN V3 [get_ports {LED[9]}]
set_property PACKAGE_PIN W3 [get_ports {LED[10]}]
set_property PACKAGE_PIN U3 [get_ports {LED[11]}]
set_property PACKAGE_PIN P3 [get_ports {LED[12]}]
set_property PACKAGE_PIN N3 [get_ports {LED[13]}]
set_property PACKAGE_PIN P1 [get_ports {LED[14]}]
set_property PACKAGE_PIN L1 [get_ports {LED[15]}]
set_property PACKAGE_PIN N19 [get_ports {red[0]}]
set_property PACKAGE_PIN J19 [get_ports {red[1]}]
set_property PACKAGE_PIN H19 [get_ports {red[2]}]
set_property PACKAGE_PIN J17 [get_ports {green[0]}]
set_property PACKAGE_PIN H17 [get_ports {green[1]}]
set_property PACKAGE_PIN G17 [get_ports {green[2]}]
set_property PACKAGE_PIN L18 [get_ports {blue[0]}]
set_property PACKAGE_PIN N18 [get_ports {blue[1]}]
set_property PACKAGE_PIN U2 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports c1]
set_property IOSTANDARD LVCMOS33 [get_ports vauxp15]
set_property IOSTANDARD LVCMOS33 [get_ports vauxp14]
set_property IOSTANDARD LVCMOS33 [get_ports vauxp7]
set_property IOSTANDARD LVCMOS33 [get_ports vauxp6]
set_property IOSTANDARD LVCMOS33 [get_ports vauxn15]
set_property IOSTANDARD LVCMOS33 [get_ports vauxn14]
set_property IOSTANDARD LVCMOS33 [get_ports vauxn7]
set_property IOSTANDARD LVCMOS33 [get_ports vauxn6]
set_property IOSTANDARD LVCMOS33 [get_ports v_sync]
set_property PACKAGE_PIN R19 [get_ports v_sync]
set_property IOSTANDARD LVCMOS33 [get_ports h_sync]
set_property PACKAGE_PIN P19 [get_ports h_sync]
set_property PACKAGE_PIN V7 [get_ports dp]
set_property PACKAGE_PIN J1 [get_ports c1]
set_property PACKAGE_PIN L2 [get_ports c2]
set_property PACKAGE_PIN J2 [get_ports c3]
set_property PACKAGE_PIN N2 [get_ports vauxp15]
set_property PACKAGE_PIN T18 [get_ports rst_btn]
set_property PACKAGE_PIN W19 [get_ports enable_btn]
set_property PACKAGE_PIN R2 [get_ports clr]
#set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports c2]
set_property IOSTANDARD LVCMOS33 [get_ports c3]
#set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clr]
set_property IOSTANDARD LVCMOS33 [get_ports dp]
set_property IOSTANDARD LVCMOS33 [get_ports rst_btn]
set_property IOSTANDARD LVCMOS33 [get_ports enable_btn]

I'm not really sure what would help in debugging this, so if any files are necessary for you guys I'll be happy to provide them. As of right now, I'm completely lost on what to do.

0

There are 0 answers