verilog assignment results in undefined 'X' output -- why?

Question

I know VHDL, and just learning verilog. I'm trying to do a simple assignment with bit shift, and I get undefined 'X' in the result. I don't understand why. This is in simulation with Xilinx ISim software.

This assignment:

assign dout = $signed(data_out >>> shift_bits);

Results in 'X' wherever a '1' should be. For example, if data_out = '00001100', and shift_bits = 1, dout will = '00000XX0'.

Below is the module definition and the assignment operation:

module SensorINV(
    input clk,
     input [23:0] din,
     input idv,
     input [4:0] shift_bits,
     output [23:0] dout,
     output reg odv
    );


reg [47:0] data_out = 0;        // initialize the output
assign dout = $signed(data_out >>> shift_bits);
// assign dout = data_out[44:21];   // this didn't work either

reg [1:0] state = 0;

always @(posedge clk) begin
    case (state)
        0   :   begin       // waiting for new data
            ...
        end
        1   :   begin
            ...
            data_out <= data_out + temp1_w;
            state <= 2;
        end
        2   :   begin
            ...
            state <= 0;
        end
        default :   state <= 0;
    endcase
end

Answer 1

The problem turned out to be conflicting drivers of dout, only one of which was shown in the code above. In the next module up, where this one was instantiated (not shown), I had a line like this:

wire [23:0] dout = 0;

This created a continuous assignment, not an initialization value. This conflict didn't show up in simulation until I tried to make dout non-zero. If it were a register reg, it would be an initialization value, but in this case it was a wire. Got rid of the continuous assign = 0, and problem solved.