Using Generate in Vhdl

Question

I have following piece of code in Vhdl now I want to redirect this signal S1 conditionally to the output port, I will be gratful if someone can guide me through this.

Gen: for index in 0 to 4 generate

 signal s1 : ARRAY_TYPE; --- array of (0 to 7) std_logic_vector (7 downto 0);
 begin  
  process(CLK)
  begin
    if (rising_edge (CLK)) then
        S1(counter_index) <= S_in((index*8+7) downto (index*8));
      end if;  
    end  if;
  end process;
end generate Gen;

I know we can use a process inside generate loop but is otherway around also possible! If I declare S1 as global signal it complains of connected to multi driven net? How this is different?

I will be really grateful if someone can guide me through this

Answer 1

Your for-generate loop (from 0 to 4) will be unrolled at elaboration so that what you end up with, effectively, is (leaving out the process code for brevity):

for index = 0:

signal s1_0 : ARRAY_TYPE; --- array of (0 to 7) std_logic_vector (7 downto 0);

s1_0(counter_index) <= S_in(7 downto 0);

for index = 1:

signal s1_1 : ARRAY_TYPE; --- array of (0 to 7) std_logic_vector (7 downto 0);

s1_1(counter_index) <= S_in(15 downto 8);

etc.

You get "copies" because you declared the signal inside the generate loop, each of which is local to just that generate block. When you try to make s1 "global" (not really global, which has a different connotation; just declared for the whole architecture), you get:

for index = 0:

s1(counter_index) <= S_in(7 downto 0);

for index = 1:

s1(counter_index) <= S_in(15 downto 8);

See what happened there? Those statements are concurrent, and assigning to the same bits. That's why you have problems with multiple drivers.

The problem appears to be counter_index. Either you need to index s1 with some combination of your loop index with your other index, as QuantumRipple suggested, or you need to create some intermediate signal, or something.

Note that if you're handling 32-bit data a byte at a time, you probably meant 0 to 3, not 0 to 4.

Answer 2

Although fru1tbat covers the solution to your problem, I wanted to cover your other question:

I know we can use a process inside generate loop but is otherway around also possible!

You can use a for ... loop inside of a process statement as well. It functions and gets unrolled similarly to a for... generate statement, but inside of a process. It can also be used to implement more complex logic by using variables or overwriting assignments. Here is a syntax reference for it: http://www.ics.uci.edu/~jmoorkan/vhdlref/for_loop.html