using a conditional variable which is defined later in verilog

Question

Suppose I have the following instantiation
first_mux_input=top.middle.down[i]; second_mux_input=top.middle.down[i+1]; assign down = (select[i])? first_mux_input:second_mux_input;

supposing there are a lot of muxes and their outputs go to the inputs to muxes that are placed below them.

I'm using the variable "down" before I define it. is this legal since verilog compiles all the lines subsequently and not by order(in this case)?
thanks

Answer 1

It depends on your synthesizer. I have worked only with Xilinx. In my case Xilinx accepts this type definition for simulation. But for synthesis you need to define a wire/reg before instantiation.

Answer 2

The assign statement is not a declaration. A declaration would be:

wire down;

If you never declare down such as this, it will be implicitly declared. Section 6.10 of IEEE 1800-2012 states:

If an identifier appears on the left-hand side of a continuous assignment statement, and that identifier has not been declared previously in the scope where the continuous assignment statement appears or in any scope whose declarations can be directly referenced from the scope where the continuous assignment statement appears (see 23.9), then an implicit scalar net of default net type shall be assumed. See 10.3 for a discussion of continuous assignment statements.

and then:

See 22.8 for a discussion of control of the type for implicitly declared nets with the `default_nettype compiler directive.

This (I believe) typically means a wire in Verilog and logic in SystemVerilog.

Now, as far as using the value before it is assigned, that's perfectly legal. As long as not declared after it is used or assigned.