Unknown Wrong result when simulating Verilog design in modelsim

Question

Design:

//structural description of 74151
module s_74151(VCC, GND, D0, D1, D2, D3, D4, D5, D6, D7, A, B, C, STROBE, Y, W);

input D0, D1, D2, D3, D4, D5, D6, D7; //data inputs
input STROBE; //enable
input A, B, C; //Data select
output Y, W; //outputs

input supply1 VCC; // logic 1 vcc supply wire
input supply0 GND; // logic 0 gnd supply wire

wire n1, n2, n3, n4, n5, n6, n7, n8; // temp AND outputs 
wire A1, A2, B1, B2, C1, C2, S1; //address buffers
wire r1; //temp NOR output

not(A1, A);
not(B1, B);
not(C1, C);
not(A2, A1);
not(B2, B1);
not(C2, C1);
not(S1, STROBE);

and(n1, D0, A1, B1, C1, S1);
and(n2, D1, A2, B1, C1, S1);
and(n3, D2, A1, B2, C1, S1);
and(n4, D3, A2, B2, C1, S1);
and(n5, D4, A1, B1, C2, S1);
and(n6, D5, A2, B1, C2, S1);
and(n7, D6, A1, B2, C2, S1);
and(n8, D7, A2, B2, C2, S1);

nor(r1, n1, n2, n3, n4, n5, n6, n7, n8);

not(Y, r1);
buf(W, r1);

endmodule

//74151 using data flow.
module d_74151(VCC, GND, D0, D1, D2, D3, D4, D5, D6, D7, A, B, C, STROBE, Y, W);

input D0, D1, D2, D3, D4, D5, D6, D7; //data inputs
input STROBE; //enable
input A, B, C; //Data select
output Y, W; //outputs

input supply1 VCC; // logic 1 vcc supply wire
input supply0 GND; // logic 0 gnd supply wire

wire n1, n2, n3, n4, n5, n6, n7, n8; // temp AND outputs 
wire A1, A2, B1, B2, C1, C2, S1; //address buffers
wire r; //temp NOR output

assign A1 = !A;
assign B1 = !B;
assign C1 = !C;
assign A2 = !A1;
assign B2 = !B1;
assign C2 = !C1;
assign S1 = !STROBE;

assign n1 = D0 && A1 && B1 && C1 && S1;
assign n2 = D1 && A2 && B1 && C1 && S1;
assign n3 = D2 && A1 && B2 && C1 && S1;
assign n4 = D3 && A2 && B2 && C1 && S1;
assign n5 = D4 && A1 && B1 && C2 && S1;
assign n6 = D5 && A2 && B1 && C2 && S1;
assign n7 = D6 && A1 && B2 && C2 && S1;
assign n8 = D7 && A2 && B2 && C2 && S1;

assign r = !(n1 || n2 || n3 || n4 || n5 || n6 || n7 || n8);

assign Y = !r;
assign W = r;

endmodule

Testbench:

`include "C:/Users/Muaz Aljarhi/Google Drive/Muaz/Hardware_Designs/Verilog Course/74151.v"

module m74151_tb();

reg D0, D1, D2, D3, D4, D5, D6, D7, A, B, C, STROBE;

wire VCCs, GNDs, VCCd, GNDd, Ys, Ws, Yd, Wd;

s_74151 s7(.VCC(VCCs), .GND(GNDs), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .A(A), .B(B), .C(C), .STROBE(STROBE), .Y(Ys), .W(Ws));

d_74151 d7(.VCC(VCCd), .GND(GNDd), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .A(A), .B(B), .C(C), .STROBE(STROBE), .Y(Wd), .W(Wd));


  initial begin

  $display("simulation started");

$monitor("Input: D0 = %b, D1 = %b, D2 = %b, D3 = %b, D4 = %b, D5 = %b, D6 = %b, D7 = %b, A = %b, B = %b, C = %b, STROBE = %b\nStructural: Y = %b, W = %b\nData Flow: Y = %b, W = %b\n", 
  D0, D1, D2, D3, D4, D5, D6, D7, A, B, C, STROBE, Ys, Ws, Yd, Wd);

  D0 = 1;
  D1 = 0;
  D2 = 1;
  D3 = 1;
  D4 = 0;
  D5 = 1;
  D6 = 0;
  D7 = 0;
  A = 0;
  B = 0;
  C = 0;
  STROBE = 1;
  #1 STROBE = 0; 

  #8  begin
  $display("simulation ended");
  $stop;
end

end

 always  #1 A = !A;
 always  #2 B = !B;
 always  #4 C = !C;

endmodule

Output result:

# simulation started
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 0, B = 0, C = 0, STROBE = 1
# Structural: Y = 0, W = 1
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 1, B = 0, C = 0, STROBE = 0
# Structural: Y = 0, W = 1
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 0, B = 1, C = 0, STROBE = 0
# Structural: Y = 1, W = 0
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 1, B = 1, C = 0, STROBE = 0
# Structural: Y = 1, W = 0
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 0, B = 0, C = 1, STROBE = 0
# Structural: Y = 0, W = 1
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 1, B = 0, C = 1, STROBE = 0
# Structural: Y = 1, W = 0
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 0, B = 1, C = 1, STROBE = 0
# Structural: Y = 0, W = 1
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 1, B = 1, C = 1, STROBE = 0
# Structural: Y = 0, W = 1
# Data Flow: Y = z, W = x
# 
# Input: D0 = 1, D1 = 0, D2 = 1, D3 = 1, D4 = 0, D5 = 1, D6 = 0, D7 = 0, A = 0, B = 0, C = 0, STROBE = 0
# Structural: Y = 1, W = 0
# Data Flow: Y = z, W = x
# 
# simulation ended

I not know why or how I got x and y values for the Y and W outputs of the d_74151 module. Although I tested and saw that r gets the correct output of 0 or 1, Y and W which depend on r still display these values in simulation. Any ideas about this and how to resolve it? Thanks in advance.

P.S. these are structural and data flow descriptions for 8 bit multiplexer/selector with enable included.

Answer 1

Your d7 instance is driving the same wire (Wd) with 2 output ports: Y and W. The Yd wire is undriven. To get rid of x on Wd, connect Yd to the Y output port.

Change:

d_74151 d7(.VCC(VCCd), .GND(GNDd), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .A(A), .B(B), .C(C), .STROBE(STROBE), .Y(Wd), .W(Wd));

to:

d_74151 d7(.VCC(VCCd), .GND(GNDd), .D0(D0), .D1(D1), .D2(D2), .D3(D3), .D4(D4), .D5(D5), .D6(D6), .D7(D7), .A(A), .B(B), .C(C), .STROBE(STROBE), .Y(Yd), .W(Wd));

It is easier to debug these errors using a debugging tool that allows tracing signals to waveforms.

Answer 2

A variable cannot have more than one continuous driver. To debug these better use waveform based approach

For eg consider the following instantiation

eg:

module top ( input a,b, output y,y1);
  assign y = a & b;
  assign y1 = a | b;
endmodule

testbench snippet:

 wire y,y1;

  top u0(.a(a),
         .b(b),
         .y(y),
         .y1(y) // y should be replaced with y1 or else 'X' will be seen in the bus
        );

Here y and y1 are connected to y, In general the default value of wire is "High Impedance(Hi-Z)" so "wire y" will be driven with y values as per instantiation .y(y) but that y value when passed to y1 which is already driving some other logical output it results in a contradiction which results in 'X'. example at EDA Playground

In your code you have connected "wire Wd" to both output Y,W in the testbench instantiation of d_74151 which caused 'X' in the output which is as expected. To resolve connect separate wires at each port of Y and W.