I am learning VHDL and I ran into the following code:
Entity fft is
port (t, r: in bit; q: out bit);
End entity;
Architecture fft_df of fft is
signal state: bit :='0';
Begin
state <='0' when r='1' else
not state when t='0' and t'event else
state;
q<=state;
End;
Well, my doubt is about what this code does and if or not this is a behavioral or dataflow description of a T flip flop with reset.
And than, which is the meaning of not state when t='0' and t'event
? (I suppose the T flip flop works on falling edge).
Thanks to all.
I'm missing the clock input. A T-flipflop (with asynchronous reset) would actually be described by
Or more commonly written as:
p.s. reading an output requires compiling in VHDL-2008 mode.