Sync two FPGAs to generate same Sine Wave

Question

I am using the Spartan 3e Xilinx FPGA board, and I am trying to sync two FPGAs to generate the same sine wave. Due to limited I/O pins there is only one connection from the Master to Slave. Is there a way to sync them up and set the phase of the sine wave? For example when the master hits zero phase a flag raises and the slave is set to zero phase too. The function prototype of the sine lut is given below. I am just starting out so any help is appreciated thank you.

sine sine_lut (
      .ce(clock_enable), // input ce
      .clk(CLK_50MHZ&& clock_enable), // input clk
     .sclr(!clock_enable),
      .pinc_in(line_freq[31:0]), // input [31 : 0] pinc_in
      .poff_in(0), // input [31 : 0] poff_in
      .sine(sine_generate[12:0]), // output [12 : 0] sine
      .phase_out(phase_out) // output [31 : 0] phase_out      
    );

Answer 1

1. The method mentioned in the question would work to some extent:

   • If the jitter of the clocks is not that big to cause a significant desynchronisation during the period of the sine wave

   • If some discontinuity in the slave output is tolerable. In order to overcome the discontinuity you can modify the method as following. Instead of just resetting the waveform, simply readjust the frequency of the signal on the slave to be slightly higher or lower for the next period, depending on whether it is too fast or too slow. You can do this using PID control technique, for example (the adjustment will be proportional to the phase error). Or simply recalculate the frequency based on the measured time between sync pulses.

2. If the sine wave frequencies are much slower than the clock frequency, you can utilise the PWM technique to encode the sine values of the master as a signal Duty Cycle, measure it on the slave and output the same value. A very small phase shift is expected, but again, it shouldn't be noticeable if the clock is much faster than the sine.