__sync_add_and_fetch triggers an sError interrupt on raspberry pi 4b

Question

When I use gcc's __sync_add_and_fetch to atomically increment an integer on my raspberry pi4b, the following code is generated:

172e4:       c85f7e60        ldxr    x0, [x19]
172e8:       91000400        add     x0, x0, #0x1
172ec:       c801fe60        stlxr   w1, x0, [x19]
172f0:       35ffffa1        cbnz    w1, 172e4 <kernel_start+0xc4>
172f4:       d5033bbf        dmb     ish

I have the MMU enabled, using normal memory with MAIR attribute 0xff. Page tables are mapped with inner & outer shareable. I am able to read/write the memory in a non-exclusive way. However when the above code runs, I get an sError interrupt (class 0x2f) at the ldxr instruction. ISS is 0x2, which according to Exception Syndrome Register, EL1 is an SLVERR on external access.

According to Arm Cortex®-M7 Processor, this happens when:

An AXI slave device in the system that cannot handle exclusive transactions returns OKAY in response to an exclusive read. This is also treated as an external error, and the processor behaves as if the response was SLVERR.

Is there something specific I need to do to enable exclusive memory transactions?

Answer 1

The answer was here:

Data caching must be enabled (SCTLR_EL1 bit [2] set to 0b1)

As soon as I enabled data caching, the atomic increment worked.