SV assertion to flag incorrect verilog event region

Question

Is there a system verilog construct which can flag an error if a signal toggled in NBA region in verilog event queue? Something like

if($toggled_in_nba(clk))
begin
     `uvm_error()
end

Answer 1

Nothing within the language. And nothing changes in the NBA region anyways—everything changes in the active region. When there are no more events in the active region, the events in the inactive region become active, potentially scheduling more events. This goes on recursively until there are no more events scheduled in the active or inactive regions. Then the events scheduled in the NBA region become active, and this loop continues until there are no more events left in any region. Only then time can advance.

Most tools have the ability to record signal changes in the same order the simulator makes them, so you can see the relative ording. But you might want to look at the XY problem to make sure you've really explained what you are trying to accomplish.